Cache memory is typically fast memory utilized to hold data temporarily as the data is moved to or from disk storage. Cache memory may consist of a number of single inline memory modules or SIMMs. Each SIMM stores a predetermined amount of data. The sum of the capacity of the individual SIMMs determines the amount of cache memory available.
Typically all such SIMM based cache memories share the following characteristics. All SIMM of a single cache memory are of the same type, either volatile or non-volatile. This "same type" requirement is generally imposed because of the different cycle times required by volatile and non-volatile memory.
All cache memory must be contiguous. This means that the base address of each SIMM (with the exception of the zero base address) must be adjacent the maximum address of a previous SIMM. Because of this requirement that memory be contiguous, if a SIMM fails and is no longer accessible, all subsequent SIMMs are also inaccessible. Thus, under certain circumstances, a failure of a single SIMM can result in the entire cache memory becoming unusable.
Finally, all SIMM addresses must be unique. The requirement is imposed because a read request must not access two different SIMMs at the same time. Therefore, if a mirror image of data is to be maintained in cache memory, at least two write requests are required.
The present invention avoids these limitations.